View IPM6220A_1699575.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 tm IPM6220A advanced triple pwm and dual linear power controller for portable applications the IPM6220A provides a highly integrated power control and protection solution for five ou tput voltages required in high- performance notebook pc applications. the ic integrates three fixed frequency pulse -width-modulation (pwm) controllers and two linear regulators along with monitoring and protection circuitry into a single 24 lead ssop package. the two pwm controllers that regulate the system main 5v and 3.3v voltages are im plemented with synchronous- rectified buck converters. sy nchronous rectification and hysteretic operation at light loads contribute to high efficiency over a wide range of input voltage and load variation. efficiency is further enhanced by using the lower mosfet?s r ds(on) as the current sense element. input voltage feed- forward ramp modulation, current-mode control, and internal feed-back compensation provide fast and stable handling of input voltage load transi ents encountered in advanced portable computer chip sets. the third pwm controller is a boos t converter that regulates a resistor selectable output voltage of nominally 12v. two internal linear regulators provide +5v always and +3.3v always low current outputs required by the notebook system controller. IPM6220A (ssop) top view features ? provides five re gulated voltages - +5v always - +3.3v always -+5v main - +3.3v main -+12v ? high efficiency over wide line and load range - synchronous buck converters on main outputs - hysteretic operation at light load ? no current-sense resistor required - uses mosfet?s r ds(on) - optional current-sense resistor for more precision ? operates directly from battery 5.6 to 22v input ? input undervoltage lock-out (uvlo) ? excellent dynamic response - voltage feed-forward and current-mode control ? monitors output voltages ? synchronous converters operate out of phase ? separate shut-down pins for advanced configuration and power interface (acpi) compatibility ? 300khz fixed switching fr equency on main outputs ? thermal shut-down protection applications ? mobile pcs ? hand-held portable instruments related literature ? application note an9915 ordering information part number temp. range ( o c) package pkg. no. IPM6220Aca -10 to 85 24 ld ssop m24.15 ipm6220eval1 evaluation board vbatt 3.3v always boot2 ugate2 vsen2 sdwn2 pgood boot1 lgate1 isen1 phase1 gnd gate3 sdwnall ugate1 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 pgnd2 phase2 isen2 vsen1 vsen3 5v always lgate2 pgnd1 sdwn1 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil and design is a trademark of intersil americas inc. copyright ? intersil americas inc. 2001, all rights reserved fn9032 data sheet june 2001 n o t r e c o m m e n d e d f o r n e w d e s i g n s r e c o m m e n d e d r e p l a c e m e n t i s l 6 2 3 2 ( a v a i l a b l e f e b . 2 0 0 4 )
2 block diagram + - ea2 ref power-on reset (por) sdwnall ramp 1 ramp 2 clk vbatt lgate2 + + - volt- clamp oc 2.8v + - d > q q r vcc boot2 ugate2 phase2 lgate2 pgnd2 vcc lgdr2 hgdr2 hi lo gate logic 2 pwm on pwm/hyst deadtime shutoff + - lgate2 r1 = 20k vsen2 isen2 - pwm latch 2 oc comp2 hyst on + - hyst comp2 clk2 clk2 clk1 + - second + - ea1 ref lgate1 + + - volt- clamp oc logic1 + - d < q q r vcc boot1 ugate1 phase1 lgate1 pgnd1 vcc lgdr1 hgdr1 hi lo gate logic 1 pwm on pwm/hyst deadtime shutoff + - lgate1 r1 = 20k vsen1 isen1 - pwm latch 1 oc comp1 hyst on + - hyst comp1 clk1 + - pwmmd1 second sdwn2 sdwn1 reference and soft start ref gnd por por 5v-always sdwn vsen1 vbatt sdwn 3.3v-always ldo1 ldo2 pgood output voltage monitor ovp2 ovp1 logic2 pwm mode 1 figure 1. pwmmd1 pwmmd2 pwmmd2 uvflt 200ns vcc uvflt 2.5v ovp1 ovp2 pwm mode 2 vsen3 gate3 clk1 boost controller ref IPM6220A
3 simplified power system diagram typical application pwm1 5v main q1 q2 linear linear pwm3 IPM6220A controller controller controller controller pwm2 controller vbatt 3.3v main q1 q2 vbatt vbatt 12v boost monitors pgood voltage, current 3.3v always 5v always figure 2. +v batt p core clock i/o v core v i/o v clock c8051 5v always 3.3v always vid code sdwn1 sdwn2 5v main 3.3v main IPM6220A ipm6210 enable sdwn sdwnall processor on/off 12v reset pgood pgood pcm cia figure 3. IPM6220A
4 absolute maximum rati ngs thermal information input voltage, vbatt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +27.0v phase, isen and sdwnall pins . . . . . . . . . . . gnd -0.3v to +27.0v boot and ugate pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +33.0v boot1, 2 with respect to phase1, 2 . . . . . . . . . . . . . . . . . . . +6.5v all other pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6.5v operating conditions input voltage, vbatt . . . . . . . . . . . . . . . . . . . . . . . . +5.6v to +24.0v ambient temperature range . . . . . . . . . . . . . . . . . . . -10 o c to 85 o c junction temperature range. . . . . . . . . . . . . . . . . . . . 0 o c to 125 o c thermal resistance (typical, note 1) ja ( o c/w) ssop package 110 maximum junction temperature (plastic package) . . . . . . . .150 o c maximum storage temperature range . . . . . . . . . . -65 o c to 150 o c maximum lead temperature (soldering 10s) . . . . . . . . . . . . .300 o c (ssop - lead tips only) caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. note: 1. ja is measured with the component mounted on a low effective ther mal conductivity test board in free air. see tech brief tb379 fo r details. electrical specifications recommended operating conditions, unless otherwise no ted. refer to block and simplified power system diagrams, and typical application schematic parameter symbol test conditions min typ max units input quiescent current i cc sdwn1 = sdwn2 = 5v, sdwnall = vin, outputs open circuited -1.42.0 ma stand-by current i ccsb sdwn1 = sdwn2 = 0v, sdwnall = vin, outputs open circuited - 300 a shut-down current i ccsn sdwnall = 0v - <1.0 a input under-voltage lock out uvlo rising vbatt 4.3 4.7 5.1 v input under-voltage lock out uvlo vbatt, hysteresis 300 mv oscillator pwm1,2 oscillator frequency f c1,2 255 300 345 khz reference and soft start internal reference voltage v ref - 2.472 - v reference voltage accuracy -1.0 - +1.0 % sdwn1, sdwn2 output current during start-up i ss -5- a pwm1 converter, 5v main output voltage v out1 5.0 v line and load regulation 0.0 < ivout1 < 5.0a; 5.6v < vbatt < 22.0v -2 0.5 +2 % under-voltage shut-down level v uv1 2 s delay, % feedback voltage at vsns1 pin 70 75 80 % current limit threshold i oc2 current from isns1 pin through rsns1 90 135 180 a over-voltage threshold v ovp1 2 s delay, % feedback voltage at vsns1 pin 110 115 120 % maximum duty cycle dc max sdwn1 > 4.0v 94 % pwm2 converter, 3.3v main output voltage vout2 3.3 v line and load regulation 0.0 < ivout2 < 5.0a; 5.6v < vbatt < 24.0v -2 0.5 +2 % under-voltage shut-down level v uv2 2 s delay, % feedback voltage at vsns2 pin 70 75 80 % current limit threshold i oc2 current from isns2 pin through rsns2 90 135 180 a over-voltage threshold v ovp2 2 s delay, % feedback voltage at vsns2 pin 110 115 120 % maximum duty cycle dc max sdwn2 > 4.0v 94 % IPM6220A
5 internal resistance to gnd on vsns2 pin r vsns2 66k ? pwm1 and pwm2 controller gate drivers upper drive pull-up resistance r 2ugpup -512 ? upper drive pull-down resistance r 2ugpdn -410 ? lower drive pull-up resistance r 2lgpup -69 ? lower drive pull-down resistance r 2lgpdn -58 ? pwm 3 converter 12v feedback regulation voltage vsen3 2.472 v 12v feedback regulation voltage input current i vsen3 0.1 1.0 a line and load regulation 0.0 < iv out3 < 120ma, 4.9v< 5vmain <5.1v -2 +2 % under-voltage shut-down level v uv3 2 s delay, % feedback voltage at vsns3 pin 70 75 80 % over-voltage threshold v ovp3 2 s delay, % feedback voltage at vsns3 pin 115 120 % pwm3 oscillator frequency f c3 85 100 115 khz maximum duty cycle 33 % pwm 3 controller gate drivers pull-up resistance r3gpup 6 12 ? pull-down resistance r3gpdn 6 12 ? 5v and 3.3v always linear regulator accuracy pwm1, 5v output off (sdwn1 = 0v); 5.6v < vbatt < 22v; 0 < i load < 50ma -2.0 0.5 +2.0 % 5v always output voltage regulation pwm1, 5v output on (sdwn1 = 5v); 0 < i load < 50ma -3.3 1.0 +2.0 % maximum output current combined 5v always and 3.3v always 50 ma current limit combined 5v always and 3.3v always 100 180 ma 5v always under-voltage shut-down 75 % bypass switch r ds(on) pwm1, 5v output on (sdwn1 = 5v) 1.3 ? power good and control functions power good threshold for pwm1 and pwm2 output voltages -14 -12 -10 % pgood leakage current i pglkg vpullup = 5.0v - - 1.0 a pgood voltage low v pgood i pgood = -4ma 0.2 0.5 v pgood minimum pulse width t pgmin 10 s sdwn1, 2 , - low (off) 0.8 v sdwn1, 2 , - high (on) 4.3 v sdwnall - high (on) 2.4 v sdwnall - low (off) sdwnall, hysteresis 40 mv over-temperature shutdown 150 o c over-temperature hysteresis 25 o c electrical specifications recommended operating conditions, unless otherwise no ted. refer to block and simplified power system diagrams, and typical application schematic (continued) parameter symbol test conditions min typ max units IPM6220A
6 functional pin descriptions vbatt (pin 1) supplies all the power necessary to operate the chip. the ic starts to operate when the voltage on this pin exceeds 4.7v and stops operating when the voltage on this pin drops below approximately 4.5v. also provides battery voltage to the oscillator for feed-forward rejection to input voltage variations. 3.3v always (pin 2) output of 3.3v always linear regulator. 5v always (pin 6) output of 5v always linear regulator or the +5v main output. if the +5v main output is enabled, it is switched internally from the vsen1 pi n to the 5v always output. this improves efficiency and reduces the power dissipation in the controller. boot1, boot2 (pins 24 and 3) power is supplied to the upper mosfet drivers of pwm1 and pwm2 converters via the boot pins. connect these pins to the respective junctions of bootstrap capacitors with the cathodes of the bootstrap diodes. anodes of the bootstrap diodes are connected to pin 6, 5v always. ugate1, ugate2 (pins 23 and 4) these pins provide the gate drive for the upper mosfets. connect ugate pins to the respective pwm converter?s upper mosfet gate. phase1, phase2 (pins 22 and 5) the phase nodes are the juncti ons of the upper mosfet sources, output filter inducto rs, and lower mosfet drains. connect the phase pins direct ly to the respective pwm converter?s lower mosfet drain. isen1, isen2 (pins 21 and 9) these pins are used to monitor the voltage drop across the lower mosfets for current feedback and current-limit protection. for more precise current detection, these inputs can be connected to optional cu rrent sense resistors placed in series with the sources of the lower mosfets. lgate1, lgate 2 (pins 20 and 7) these pins provide the gate drive for the lower mosfets. connect the lower mosfet gate of each converter to the corresponding pin. pgnd1, pgnd2 (pins 19 and 8) these are the lower mosfet gate drive return connection for pwm1 and pwm2 converters, respectively. tie each lower mosfet source directly to the corresponding pin. vsen1, vsen2 (pins 18, 10) these pins are connected to the main outputs and provide the voltage feedback signal for the respective pwm controllers. the pgood, over voltage protection (ovp) and undervoltage shutdown circuits use these signals to determine output-voltage st atus and/or to initiate undervoltage shut down. the vsen1 input is also switched internally to the 5v always out put if the +5v main output is enabled. sdwnall (pin 13) this pin provides enable/disable function for all outputs. the chip is completely disabled when this pin is pulled to ground. when this pin is pulled high, the 5v always and 3.3 always outputs are on and t he other outputs are enabled. the state of 5v main and 3.3v main outputs depend on the voltage on sdwn1 and sdwn2 respectively. see table 1. sdwn1 (pin 17) this pin provides enable/disable function and soft-start for the pwm1, 5v main, output. the output is enabled when this pin is high and sdwnall is also high. the 5v output is held off when the pin is pulled to the ground. sdwn2 (pin 11) this pin provides enable/disable function and soft-start for pwm2, 3.3v main, output. the output is enabled when this pin is high and sdwnall is also high. the 3.3v output is held off when the pin is pulled to the ground. vsen3 (pin 15) this input pin is the voltage feedback signal for pwm3, the boost controller. the boost controller regulates this point to a voltage divided level of 2.472 vdc. the pgood, overvoltage protection (ovp) and undervoltage shutdown circuits use this signal to det ermine output-voltage status and/or to initiate undervoltage shut down. this pin can also be used to independently disable the pwm3 controller. connect this pin to 5v always if the boost converter is not populated in your design. gate3 (pin 16) this pin drives the gate of the boost mosfet. pgood (pin 12) pgood is an open drain output used to indicate the status of the pwm converters? output voltages. this pin is pulled low when any of the outputs except pwm3 (12v) is not within -10% of respective nominal voltages, or when pwm3 (12v) is not within its undervoltage and overvoltage thresholds. gnd (pin 14) signal ground for the ic. all voltage levels are measured with respect to this pin. general description the IPM6220A addresses th e system electronics power needs of modern notebook and sub-notebook pcs. the ic integrates control circuits for two synchronous buck IPM6220A
7 converters for 5v main and 3.3v main buses, two linear regulators for 3.3v always and 5v always, and a 12v boost converter. the two synchronous converters operate out of phase to substantially reduce the input-c urrent ripple, minimizing input filter requirements, minimi zing battery heating and prolonging battery life. the 12v boost controller uses a 100khz clock derived from the main clock. this controll er uses leading edge modulation with the maximum duty cycle limited to 33%. the chip has three input control lines sdwn1 , sdwn2 and sdwnall . these are provided for advanced configuration and power interface (acpi) compatibility. they turn on and off all outputs, as well as prov ide independent control of the 3.3v main and +5v main outputs. to maximize efficiency for the 5v main and 3.3v main outputs, the current-sense technique is based on the lower mosfet r ds(on). light-load efficiency is further enhanced by a hysteretic mode of operation wh ich is automatically engaged at light loads when the inductor current becomes discontinuous. 3.3v main and 5v main architecture these main outputs are gener ated from the unregulated battery input by two independent synchronous buck converters. the ic integrates all the components required for output voltage setpoint and feedback compensation, significantly reducing the number of external components, saving board space and parts cost. the buck pwm controllers employ a 300khz fixed frequency current-mode control scheme with input voltage feed- forward ramp programming for better rejection of input voltage variations. figure 4 shows the out-of-phase operation for the 3.3v main and 5v main outputs. the phase node is the junction of the upper mosfet, lower mosfet and the output inductor. the phase node is high when the upper mosfet is conducting and the inductor current rises accordingly. when the phase node is low, the lower mosfet is conducting and the inductor current is ramping down as shown. current sensing and current limit protection both pwm converters use the lower mosfet on-state resistance, r ds(on) , as the current-sensing element. this technique eliminates the need fo r a current sense resistor and the associated power losses. if more accurate current protection is desired, current sense resistors may be used in series with the lower mosfets? source. to set the current limit, place a resistor, rsns, between the isen inputs and the drain of the lower mosfet (or optional current sense resistor). the required value of the rsns resistor is determined from the following equation: where iocdc is the desired dc overcurrent limit; rcs is either the r ds(on) of the lower mosfet, or the value of the optional current-sense resistor, vo is the output voltage and l is the output inductor. also, the value of rcs should be specified for the expec ted maximum operating temperature. the sensed voltage, and the resulting current out of the isen pin through rsns, is used for current feedback and current limit protection. this is compared with an internal current limit threshold. when a sampled value of the output current is determined to be above the current limit threshold, the pwm drive is terminated and a counter is initiated. this limits the inductor current build-up and essentially switches the converter into cu rrent-limit mode. if an overcurrent is detected between 26 s to 53 s later, an overcurrent shutdown is in itiated. if during the 26 s to 53 s period, an overcurrent is not detected, the counter is reset and sampling continues as normal. this current limit scheme has proven to be very robust in applications like portable comp uters where fast inductor current build-up is common due to a large difference between input and output voltages and a low value of the inductor. light-load (hysteretic) operation in the light-load (hysteretic) mode the output voltage is regulated by the hysteretic co mparator which regulates the output voltage by maintaining the output voltage ripple as shown in figure 5. in hyster etic mode, the inductor current flows only when the output voltage reaches the lower limit of the hysteretic comp arator and turns off at the upper limit. hysteretic mode saves converte r energy at light loads by supplying energy only at the time when the output voltage requires it. this mode conser ves energy by reducing the power dissipation associated with continuous switching. rsns rcs 135 a ----------------- - iocdc vo l2300khz ---------------------------------------- - + ?? ?? 100 ? = 0 a, v 0 a, v 5v phase (10v/div.) 1 s/div. i l3.3v (2a/div.) i l5v (2a/div.) 5a 5a v in = 10.8v 3.3v phase (10v/div.) figure 4. out of phase operation IPM6220A
8 during the time between inductor current pulses, both the upper and lower mosfets are turned off. this is referred to as ?diode emulation mode? because the lower mosfet performs the function of a diode. this diode emulation mode prevents the output capacitor from discharging through the lower mosfet when the upper mosfet is not conducting. the gate drive is synchronized to the main clock, so the out- of-phase timing is maintained in hysteretic mode. such a scheme insures a seamless transition between the operational modes. operation-mode control the mode-control circuit chan ges the converter?s mode of operation based on the voltage polarity of the phase node when the lower mosfet is conducting and just before the upper mosfet turns on. for continuous inductor current, the phase node is negative when the lower mosfet is conducting and the converters operate in fixed-frequency pwm mode as shown in figure 6. when the load current decreases to the point where the inductor current flow through the lower mosfet in the ?reverse? direction, the phase node becomes positive, and the mode is changed to hysteretic. a phase comparator handles the timing of the phase node voltage sensing. a low level on the phase comparator output indicates a negative phase voltage during the conduction time of the lower mosfet. a high level on the phase comparator output indicate s a positive phase voltage. when the phase node is positive (phase comparator high), at the end of the lower mosf et conduction time, for eight consecutive clock cycles, the mode is changed to hysteretic as shown in figure 6. the dashed lines indicate when the phase node goes positive and the phase comparator output goes high. the solid vertical lines at 1,2,...8 indicate the sampling time, of the phase comparator, to determine the polarity (sign) of the phase n ode. at the transition between pwm and hysteretic mode both the upper and lower mosfets are turned off. the phase node will ?ring? based on the output inductor and the parasitic capacitance on the phase node and settle out at the value of the output voltage. the mode change from hysteretic to pwm can be caused by one of two events. one event is the same mechanism that causes a pwm to hysteretic tran sition. but instead of looking for eight consecutive positive occurrences on the phase node, it is looking for eight consecutive negative occurrences on the phase node. the operation mode will be changed from hysteretic to pwm when these eight consecutive pulses occur. this transition technique prevents jitter of the operation mode at load levels close to boundary. the other mechanism for changing from hysteretic to pwm is due to a sudden increase in the output current. this step load causes an instantaneous decrease in the output voltage due to the voltage drop on the output capacitor esr. if the decrease causes the output voltage to drop below the hysteretic regulation level, the mode is changed to pwm on the next clock cycle. this insures the full power required by the increase in output current. gate control logic the gate control logic transl ates generated pwm control signals into the mosfet gate drive signals providing necessary amplification, level shifting and shoot-through protection. also, it has functions that help optimize the ic performance over a wide range of operational conditions. since mosfet switching time can vary dramatically from type to type and with the input voltage, the gate control logic provides adaptive dead time by monitoring the gate-to- source voltages of both upper and lower mosfets. the lower mosfet is not turned on until the gate-to-source voltage of the upper mosfet has decreased to less than approximately 1 volt. similarly, the upper mosfet is not turned on until the gate-to-s ource voltage of the lower mosfet has decreased to less than approximately 1 volt. this allows a wide variety of upper and lower mosfets to be used without a concern for simultaneous conduction, or shoot-through. pwm hysteretic 1 2 3 4 5 6 7 8 vout i l phase comp operation mode of t t t t figure 5. regulation in hysteretic mode pwm hysteretic 1 2 3 4 5 6 7 8 i l phase comp operation mode of t t t phase node t figure 6. mode control waveforms IPM6220A
9 3.3v main and 5v main soft start, sequencing and stand-by see table 1 for the output voltage control algorithm. the 5v main and 3.3v main converters are enabled if sdwn1 and sdwn2 are high and sdwnall is also high. the stand-by mode is defined as a condition when sdwn1 and sdwn2 are low and the pwm converters are disabled but sdwnall is high (3.3v always and 5v always outputs are enabled). in this power saving mode, only t he low power micro-controller and keyboard may be powered. soft start of the 3.3v main and 5v main converters is accomplished by means of capacitors connected from pins sdwn1 and sdwn2 to ground. in conjunction with 5 a internal current sources, they provide a controlled rise of the 3.3v main and 5v main output voltages. the value of the soft-start capacitors can be calculated from the following expression. where tss is the desired soft-start time. by varying the values of the soft-start capacitors, it is possible to provide sequencing of the main outputs at start-up. figure 7 shows the soft-start initiated by the sdwnall pin being pulled high with the vbatt input at 10.8v and the resulting 3.3v main and 5v main outputs. while the sdwnall pin is held low, prior to t0, all outputs are off. pulling sdwnall high enables the 3.3v always and 5v always outputs. with the 3.3v main and 5v main outputs enabled, at t1, the internal 5 a current sources start charging the soft start capacitors on the sdwn1 and sdwn2 pins. at t2 the outputs begin to rise and because they both have the same value of soft-start capacitors, 0.022 f, they both reach regulation at the same time, t3. the soft-start capacitors continue to charge and are completely charged at t4. 12v converter architecture the 12v boost converter generates its output voltage from the 5v main output. an external mosfet, inductor, diode and capacitor are required to complete the circuit. the output signal is fed back to the controller via an external resistive divider. the boost controller can be disabled by connecting the vsen3 pin to 5v always. the control circuit for the 12v converter consists of a 3:1 frequency divider which drives a ramp generator and resets a pwm latch as shown in figure 8. the width of the clk/3 pulses is equal to the period of the main clock, limiting the duty cycle to 33%. the output of a non-inverting error amplifier is compared with the ri sing ramp voltage. when the ramp voltage becomes higher than the error signal, the pwm comparator sets the latc h and the output of the gate driver is pulled high providing leading edge, voltage mode pwm. the falling edge of the clk/3 pulses resets the latch and pulls the output of the gate driver low. the 33% maximum duty cycle of the converter guarantees discontinuous inductor current and unconditional stability over all operating conditions. the boost converter with th e limited duty cycle and discontinuous inductor current can deliver to the load a limited amount of power before the output voltage starts to drop. when the duty cycle has reached dmax, the control table 1. output voltage control sdwnall sdwn1 sdwn2 3v and 5v always 5v main 3v main 0xxoffoffoff 100onoffoff 110ononoff 101onoffon 111ononon css 5 atss 3.5v ---------------------------- = sdwn2, 2v/div. 3.3v out , 2v/div. 5v out , 2v/div. 0v 0v 4ms/div. sdwn1, 2v/div. t0 t1 t2 t3 t4 sdwnall ,10v/div . v in = 10.8v figure 7. soft start on 3.3v and 5v outputs - ea3 ref + q q r s pwm latch 3 vsen3 + - clk divider 3:1 ramp generator clk/3 clk/3 gate3 ramp t t t t clk clk/3 ramp vea3 gate3 pwm comparator figure 8. 12v boost operation IPM6220A
10 loop is operating open circuit and the output voltage varies with the output load resistance, ro, as given by: where vin is the 5v main voltage, dmax = 0.33, l is the value of the boost inductor, l3, and f = 100khz. this provides automatic output current limiting. when the maximum duty cycle has been reached and for a given inductor, a further reduction in ro by one-half will pull the output voltage down to 0.707 of nominal and cause an under-voltage condition. the 12v converter starts to operate at the same time as the 5v main converter. the rising voltage on the 5v main output and the 33% duty cycle limit provi des a similar soft-start, as the 5v main, for the 12v output. 3v always, 5v always linear regulators the 3.3v always and 5v always outputs are derived from the battery voltage and are the first voltages available in the notebook when power on is initiated. the 5v always output is generated directly fr om the battery voltage by a linear regulator. it is used to power the system micro- controller and to internally power the chip and the gate drivers. the 3.3v always output is generated from the 5v always output and may be used to power the keyboard controller or other peripherals. the combined current capability of these outputs is 50ma. when the 5v main output is greater than it ?s undervoltage level, it is switched to the 5v always output via an internal 1.3 ? mosfet switch. simultaneously, the 5v always linear regulator is disabled to prevent excessive power dissipation. the rise time of the 5v always is determined by the value of the output capacitance on the 5v and 3.3v always outputs. the internal regulator is current limited to about 180ma, so the start up time is approximately: where c out is the sum of the capacitances on the 5v and 3.3v always outputs. power good status the IPM6220A monitors all the output voltages except for the 3.3v always. a single power-good signal, pgood, is issued when soft-start is completed and all monitored outputs are within 10% of their respective set points. after the soft-start sequence is completed, undervoltage protection latches the chip off when any of the monitored outputs drop below 75% of its set point. a ?soft-crowbar? function is implemented for an overvoltage on the 3.3v main or 5v main outputs. if the output voltage goes above 115% of their nominal output level, the upper mosfet is turned off and the lower mosfet is turned on. this ?soft-crowbar? condition will be maintained until the output voltage returns to the regulation window and then normal operation will continue. this ?soft-crowbar? and monitoring of the output, prevents the output voltage from ringing negative as the inductor current flows in the ?reverse? direction through the lower mosfet and output capacitors. over-temperature protection the ic incorporates an over-t emperature protection circuit that shuts all the outputs down when the die temperature exceeds 150 o c. normal operation is automatically restored when the die temperature cools to 125 o c. component selection guidelines output capacitor selection the output capacitors for each output have unique requirements. in general, the output capacitors should be selected to meet the dynamic regulation requirements including ripple voltage and load transients. 3.3v main and 5v main pwm output capacitors selection of the output capacitors is also dependent on the output inductor so some inductor analysis is required to select the outpu t capacitors. one of the parameters limiting the converter?s response to a load transient is the time required for the inductor current to slew to it?s new level. given a sufficiently fast control loop design, the IPM6220A will provide either 0% or 94% duty cycle in response to a load transient. the response time is the time interval required to slew the inductor current from an initial current value to the load current level. during this interval the difference between the inductor current and the transient current level must be supplied by the output capacitor(s). minimizing the re sponse time can minimize the output capacitance required. also , if the load transient rise time is slower than the inductor response time, as in a hard drive or cd drive, this reduce s the requirement on the output capacitor. the maximum capacitor value required to provide the full, rising step, transient load curre nt during the response time of the inductor is: where: c out is the output capacitor(s) required, l o is the output inductor, i tran is the transient load current step, v in is the input voltage, v out is output voltage, and ? v out is the drop in output voltage allowed during the load transient. high frequency capacitors initially supply the transient current and slow the load rate-of-change seen by the bulk capacitors. the bulk filter capacitor values are generally determined by the esr (equivalent series resistance) and vo vin dmax ro 2lxf () ------------------- ?? ?? = tc out 5v 180ma ------------------- = c out l o i tran v in v out ? () 2 ---------------------------------------------- i tran dv out -------------------- = IPM6220A
11 voltage rating requirements as well as actual capacitance requirements. the output voltage ripple is due to the inductor ripple current and the esr of the output capacitors as defined by: where, ? i l is calculated in the inductor selection section. high frequency decoupling capacitors should be placed as close to the power pins of the load as physically possible. be careful not to add inductance in the circuit board wiring that could cancel the usefulness of these low inductance components. consult with the manufacturer of the load circuitry for specific decoupling requirements. use only specialized low-esr capacitors intended for switching-regulator applicati ons, at 300khz, for the bulk capacitors. in most ca ses, multiple electrolytic capacitors of small case size perform better than a single large case capacitor. the stability requirement on the selection of the output capacitor is that the ?esr zero?, f z , be between 1.2khz and 30khz. this range is set by an internal, single compensation zero at 6khz. the esr zero can be a factor of five on either side of the internal zero and still contribute to increased phase margin of the control loop. therefore: in conclusion, the output capacito rs must meet three criteria: by varying the values of the soft-sta rt capacitors, it is possible to provide sequencing of the main outputs at start-up. 1. they must have sufficient bulk capacitance to sustain the output voltage during a load transient while the output inductor current is slewing to the value of the load transient 2. the esr must be sufficiently low to meet the desired output voltage ripple due to the output inductor current, and 3. the esr zero should be placed, in a rather large range, to provide additional phase margin. 3.3v always and 5v always output capacitors the output capacitors for the linear regulators insure stability and provide dynamic load current. the 3.3v always and the 5v always linear regulators should have, as a minimum, 10 f capacitors on their outputs. 3.3v main and 5v main pwm output inductor selection the pwm converters require output inductors. the output inductor is selected to meet the output voltage ripple requirements. the inductor value determines the converter?s ripple current and the ripple voltage is a function of the ripple current and output capacitor(s) esr. the ripple voltage expression is given in the capacitor selection section and the ripple current is approximated by the following equation: input capacitor selection the important parameters for t he bulk input capacitor(s) are the voltage rating and the rms current rating. for reliable operation, select bulk input capacitors with voltage and current ratings above the maximum input voltage and largest rms current required by the ci rcuit. the capacitor voltage rating should be at least 1.25 times greater than the maximum input voltage and 1.5 times is a conservative guideline. the ac rms input current varies with load as shown in figure 9. depending on the specif ics of the input power and it?s impedance, most (or all) of this current is supplied by the input capacitor(s). figure 9 also shows the advantage of having the pwm converters oper ating out of phase. if the converters were operating in phase, the combined rms current would be the algebraic su m, which is a much larger value as shown. the combined out-of-phase current is the square root of the sum of the square of the individual reflected currents and is signif icantly less than the combined in-phase current. use a mix of input bypass capaci tors to control the voltage ripple across the mosfets. us e ceramic capacitors for the high frequency decoupling and bulk capacitors to supply the rms current. small ceramic capa citors can be placed very close to the upper mosfet to suppress the voltage induced in the parasitic circuit impedances. for board designs that allow through-hole components, the sanyo os-con? series offer low esr and good temperature performance. for surface mount designs, solid tantalum capacitors can be used, but caution must be ex ercised with regard to the capacitor surge current rating . these capacitors must be capable of handling the surge-current at power-up. the tps series available from avx is surge current tested. v ripple ? i l esr = c out 1 2 esr f z ------------------------------------------- = ? i l v in v out ? f s l ------------------------------- - v out v in --------------- - = figure 9. input rms current vs load 12345 3.3v and 5v load current input rms current 5 4.5 4 3.5 3 2.5 2 1.5 1 0.5 0 0 in phase out of phase 3.3v 5v IPM6220A os-con? is a registered trademark of sanyo electric company, ltd. (japan)
12 +12v boost converter inductor selection the inductor value is chosen to provide the required output power to the load. where, vinmin is the minimum input voltage, 4.9v; dmax = 1/3, the maximum duty cycle; ro is the minimum load resistance; vo is the nominal output voltage and f is the switching frequency, 100khz. +12v boost converter output capacitor selection the total capacitance on the 12v output should be chosen appropriately, so that the output voltage will be higher than the undervoltage limit (9v) when the 5v main soft-start time has elapsed. this will avoid triggering of the 12v undervoltage protection. the maximum value of the boost capacitor, comax that will charge to 9v in the soft start time, tss, is shown below, where l is the value of the boost inductor. the output capacitor esr and the boost inductor ripple current determines the output voltage ripple. the ripple voltage is given by: and the maximum ripple current, ? i l, is given by: where l is the boost inductor calculated above, 5v is the boost input voltage and 3.3 is the maximum on time for the boost mosfet. mosfet considerations the logic level mosfets are chosen for optimum efficiency given the potentially wide input voltage range and output power requirements. two n-channel mosfets are used in each of the synchronous-rectif ied buck converters for the pwm1 and pwm2 outputs. these mosfets should be selected based upon r ds(on) , gate supply requirements, and thermal management considerations. the power dissipation includes two loss components; conduction loss and switching loss. these losses are distributed between the upper and lower mosfets according to duty cycle (see the following equations). the conduction losses are the main component of power dissipation for the lower mosfets. only the upper mosfet has significant switching losses, since the lower device turns on and off into near zero voltage. the equations assume linear voltage-current transitions and do not model power loss due to the reverse-recovery of the lower mosfet?s body diode. the gate-charge losses are dissipated by the IPM6220A a nd do not heat the mosfets. however, a large gate-charge increases the switching time, t sw which increases the upper mosfet switching losses. ensure that both mosfets are within their maximum junction temperature at high ambient temperature by calculating the temperature rise according to package thermal-resistance specifications. layout considerations mosfets switch very fast and efficiently. the speed with which the current transitions from one device to another causes voltage spikes across the interconnecting impedances and parasitic circuit elements. the voltage spikes can degrade efficiency, radiate noise into the circuit, and lead to device overvoltage stress. careful component layout and printed circuit design minimizes the voltage spikes in the converter. consider, as an example, the turn-off transition of one of the upper pwm mosfets. prior to turn-off, the upper mosfet is carrying the full lo ad current. during the turn-off, current stops flowing in the upper mosfet and is picked up by the lower mosfet. any inductance in the switched current path generates a voltage spike during the switching interval. careful component selection, tight layout of the critical components, and short, wide circuit traces minimize the magnitude of voltage spikes. see the application note an9915 for the evaluation board component placement and the printed circuit board layout details. there are two sets of critical components in a dc-dc converter using an IPM6220A controller. the switching power components are the most critical because they switch large amounts of energy, and as such, they tend to generate equally large amounts of nois e. the critical small signal components are those connected to sensitive nodes or those supplying critical bias currents. power components layout considerations the power components and the controller ic should be placed first. locate the input ca pacitors, especially the high- frequency ceramic decoupling ca pacitors, close to the power mosfets. locate the output i nductor and output capacitors between the mosfets and the load. locate the pwm controller close to the mosfets. insure the current paths from the input capacitors to the mosfets, to the output inductors and output capacitors are as short as possible with maximum allowable trace widths. a multi-layer printed circuit board is recommended. dedicate one solid layer for a ground plane and make all critical component ground connections with vias to this layer. dedicate another solid layer as a power plane and break this plane into smaller islands of common voltage levels. the lmax vinmin 2 dmax 2 ro 2vo 2 f ---------------------------------------------------------------- = comax tss l ---------- 0.115 f = v ripple ? i l esr = ? i l 5v l ------- 3.3 = p upper i o 2 r ds on () v out v in ------------------------------------------------------------ i o v in t sw f s 2 ---------------------------------------------------- + = p lower i o 2 r ds on () v in v out ? () v in -------------------------------------------------------------------------------- - = IPM6220A
13 power plane should support the input power and output power nodes. use copper filled polygons on the top and bottom circuit layers for the phase nodes, but do not unnecessarily oversize these particular isla nds. since the phase nodes are subjected to very high dv/dt voltages, the stray capacitor formed between these islands and the surrounding circuitry will tend to couple switching no ise. use the remaining printed circuit layers for small signal wiring. the wiring traces from the control ic to the mosfet gate and source should be sized to carry 2a peak currents. small components signal layout considerations 4. the vsns1 and vsns2 inputs should be bypassed with a 1.0 f capacitor close to their respective ic pins. 5. a ?t? filter consisting of a ?s plit? rsns and a small, 100pf, capacitor as shown in figure 10, may be helpful in reducing noise coupling into the isen input. for example, if the calculated value of rsns1 is 2.2k ? , dividing it as shown with a 100pf capacitor provides filtering without changing the current limit set point. for any calculated value of rsns, keep the value of the r9 portion to approximately 200 ? , and the remainder of the resistance in the r19 position. the 200 ? resistor and 100pf capacitor provide effective f iltering for noise above 8mhz. this filter configuration may be helpful on both the 3.3v and 5v main outputs. 6. the bypass capacitors for vbatt and the soft-start capacitors, c ss1 and c ss2 should be located close to their connecting pins on the control ic. minimize any leakage current paths from sdwn1 and sdwn2 nodes, since the internal current source is only 5 a. 7. refer to the application note an9915 for a recommended component placement and interconnections. figure 11 shows an application circuit of a power supply for a notebook pc microprocesso r system. the power supply provides +5v always, +3.3v always, +5.0v, +3.3v, and 12v from +5.6-22v dc battery voltage. for detailed information on the circuit, including a bill of materials and circuit board description, see application note an9915. also see intersil?s web site (www.intersil.com) for the latest information. isen1 r19 r9 200 2k c12 100pf from phase node rsns = r19 + r9 figure 10. noise filter for isen1 input sdwnall gnd +5.6-22v in pgnd1 lgate1 ugate1 isen1 phase1 q3 q5 +3.3v vsen2 ugate2 phase2 q2 c1 IPM6220A l2 + + + c4 c3, 6, 10 r9, 19 +5v 100 f c22 330 f l1 huf76112sk8 56 f 3x1 f huf76112sk8 2x330 f 2.2k 8.2 h 8.2 h gnd (5a) 4 5 10 2 6 1 21 23 22 20 19 17 13 14 c9 0.15 f boot1 pgnd2 lgate2 q4 huf76112sk8 7 8 isen2 r10, 11 2.2k 9 c7 0.15 f boot2 vbatt + 3.3v always 3.3v always 5v always 11 sdwn2 c21, 32 d2 d1 24 3 huf76112sk8 bat54wt1 (5a) (50ma) +5v always (50ma) c2 + 10 f 0.022 f 12 pgood 18 sdwn1 0.022 f c17 16 l4 2.7 h c16 q5 + 15 vsen3 gate3 vsen1 huf76112sk8 c24, 33 2x47 f d3 r14 97.6k 24.9k r13 bat54wt1 + l3 6.8 h 22 f c36 figure 11. applications circuit +12v (120ma) IPM6220A
14 IPM6220A
15 all intersil semiconductor products are manufactured, assembled and tested under iso9000 quality systems certification. intersil semiconductor products are sold by description only. intersil corporation reserves the right to make changes in circui t design and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reli- able. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of patents o r other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see web site www.intersil.com IPM6220A shrink small outline plastic packages (ssop) notes: 1. symbols are defined in the ?mo series symbol list? in section 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ?d? does not include mo ld flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e? does not include inte rlead flash or protrusions. inter- lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual in- dex feature must be located within the crosshatched area. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. dimension ?b? does not include dam bar protrusion. allowable dam- bar protrusion shall be 0.10mm (0.004 inch) total in excess of ?b? dimension at maximum material condition. 10. controlling dimension: inches. c onverted millimeter dimensions are not necessarily exact. index area e d n 123 -b- 0.17(0.007) c a m bs e -a- b m -c- a1 a seating plane 0.10(0.004) h x 45 o c h 0.25(0.010) b m m l 0.25 0.010 gauge plane a2 m24.15 24 lead thin shrink narrow body small outline plastic package symbol inches millimeters notes min max min max a 0.053 0.069 1.35 1.75 - a1 0.004 0.010 0.10 0.25 - a2 - 0.061 - 1.54 - b 0.008 0.012 0.20 0.30 9 c 0.007 0.010 0.18 0.25 - d 0.337 0.344 8.55 8.74 3 e 0.150 0.157 3.81 3.98 4 e 0.025 bsc 0.635 bsc - h 0.228 0.244 5.80 6.19 - h 0.0099 0.0196 0.26 0.49 5 l 0.016 0.050 0.41 1.27 6 n24 247 0 o 8 o 0 o 8 o - rev. 0 12/00

▲Up To Search▲

Price & Availability of IPM6220A

	To Download IPM6220A Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .